The analog front end (AFE) is the measurement block of the smart-meter SoC. It samples the mains voltage and current 4,000 times per second and delivers each sample as a signed 24-bit word, from which the processor computes power and energy. This page traces the signal through each block of the Dolphin Metro-PM-MFE, using one worked example throughout.
All charts and calculations use the same operating point, so every value can be traced from input to output.
The AFE samples the mains voltage and current 4,000 times per second and outputs each sample as a signed 24-bit number. The chain has six stages:
The AFE inputs accept only a few hundred millivolts. Board components scale the 230 V mains and the load current down to that level: a resistor divider for voltage and a current transformer (CT) with a burden resistor for current. A 1 kΩ / 10 nF anti-alias RC filter on each pin removes high-frequency noise before sampling.
The sensors scale the mains down to the millivolt range and keep the waveform shape unchanged. The resistor divider attenuates the voltage by 1,500. The CT produces a secondary current 2,500 times smaller than the load current, and the 10 Ω burden resistor converts that current into a voltage.
230 V is the rms value. The peak of the sine wave is √2 × 230 = 325 V, which is why the voltage chart spans ±325 V.
| Item | Value | Source |
|---|---|---|
| V pin limit | ±300 mV peak, 212 mV rms (SENSOR_VP) | §3.2.2.1 |
| I/T pin limit at ×8 | ±275 mV peak diff, 194 mV rms | §3.2.2.1 |
| Anti-alias RC | RAA 1 kΩ, CAA 10 nF → 15.9 kHz corner, 0.18° lag at 50 Hz on every pin (ignored in the charts) | §1.2 |
| Divider 1:1500, CT 2500:1, burden 10 Ω | example board values | example |
| Pins | SENSOR_VP/VN, SENSOR_IP/IN, SENSOR_TP/TN | §2 |
The Σ-Δ converter in Step 3 has a fixed input range. A signal that uses too little of it is degraded by noise; a signal that exceeds it is clipped. The voltage signal is already well sized, so it passes through a unity-gain buffer. The current signal is small, so a programmable gain amplifier (PGA) raises it. The gain is fixed at configuration time; this example uses ×8.
Each channel has a maximum input. V: 300 mV. I at gain ×8: 275 mV.
% of range = signal ÷ maximum. V at its top: 216.8 ÷ 300 = 72 %. I at its top: 56.6 ÷ 275 = 21 %. 100 % is the limit; above it the signal is clipped.
Why the PGA is needed. The PGA multiplies the current signal and its limit by 8 (56.6 → 453 mV, 275 → 2,200 mV), so the percentage stays 21 %. Without the ×8, the current would fill only 56.6 ÷ 2,200 = 2.6 % of the converter, too little to stay clear of its noise.
| PGA gain | 10 A uses | Current that fills 100 % | Good for a meter rated up to |
|---|---|---|---|
| ×4 | 10 % | 97 A | 60–80 A |
| ×8 (this page) | 21 % | 48 A | 40 A |
| ×16 | 41 % | 24 A | 20 A |
| ×32 | 83 % | 12 A | 10 A |
| Item | Value | Source |
|---|---|---|
| PGA_GAIN_I / _T (0x27) | 010 ×4 (reset) · 011 ×8 · 100 ×16 · 101 ×32 | §7.6.12 |
| V path | unity-gain buffer, no PGA | §1.1 |
| Low-power mode | PGAs bypassed, ×1 on all paths, ±1.1 V peak | §3.2.2.2 |
| Gain error | ±1 % raw, <0.1 % after GAIN_ERR_x | §3.3.1 |
| Amplifier output values | nominal Vin × gain (V ×1, I ×8). Dolphin does not publish the internal node voltage or the modulator full scale; 2,200 mV is the pin limit × gain | not in spec |
The Σ-Δ modulator is the analog-to-digital converter. At 1,024,000 samples per second (one clock tick every 0.977 µs) it outputs a single bit, 1 or 0. The proportion of 1s tracks the input: mostly 1s near the positive peak, mostly 0s near the negative peak, and an even mix at zero. Individual bits have no meaning on their own; the density of 1s represents the signal.
The modulator runs continuously and has no notion of "256". The grouping into blocks of 256 bits happens in Step 4, because the modulator produces 1,024,000 bits/s and the output rate is 4,000 words/s: 1,024,000 ÷ 4,000 = 256 bits per word.
The modulator outputs one bit per clock tick at 1.024 MHz. The density of 1s follows the input: 50 % 1s at zero input, 100 % at +full scale, 0 % at −full scale. A single bit carries no information; the average over many bits does.
Density of 1s = 50 % + (signal % ÷ 2). At the voltage peak (+72.3 %) this gives 86 %.
Feedback is the previous bit converted back to a voltage (1 → +300 mV, 0 → −300 mV) and subtracted from the input; it pulls the running total back toward zero. The previous bit only sets the feedback; the next bit depends on the running total, which carries the history of all earlier ticks.
Table: first 16 of the 256 ticks in one 0.25 ms slot (the loop runs continuously). Each tick uses one feedback value, set by the previous tick's bit: +300 mV after a 1, −300 mV after a 0.
Illustration uses a first-order loop with ±300 mV feedback (V channel full scale). Dolphin does not state the modulator order; a higher-order loop gives a different bit pattern but the same average.
| Item | Value | Source |
|---|---|---|
| Modulator clock | MCLK/4 = 4.096 MHz/4 = 1.024 MHz | §3.2.1, §5.3 |
| Channels | 3 modulators (V, I, T), all synchronous to MCLK | §1.1 |
| See the raw bits | TR1_x.DIG_BYPASS_x = 1 → PDM on MFE_SDATA_x, 1.024 MHz | §5.3 |
| Modulator order, full-scale mapping | not given. Bits on this page come from a simple 1st-order model with ±100 % of range = all 1s / all 0s | not in spec |
| SNR | 99 dB min / 103 dB typ at ×4, 1–60 Hz | §3.3.2 |
The 1-bit stream is not directly usable by a processor. The decimation filter divides time into 0.25 ms slots, each containing 256 bits (1,024,000 ÷ 4,000), and produces one 24-bit two's-complement word per slot. One 20 ms mains cycle therefore yields 80 words per channel.
Bits per word. The modulator produces 1,024,000 bits/s and the output rate is 4,000 words/s, so each word is built from 1,024,000 ÷ 4,000 = 256 bits. These 256 bits span 0.25 ms, so one 20 ms mains cycle yields 20 ÷ 0.25 = 80 words.
Bit count to signal level. Weight each 1 as +1 and each 0 as −1, sum, and divide by 256. With 220 ones and 36 zeros: (220 − 36) ÷ 256 = +71.9 % of full scale. An even split of 128/128 gives 0 %.
Signal level to output code. Multiply by the channel's full-scale code, 603,980 for V (1,006,633 × 0.3 V × 2, Dolphin Table 3.2). for the slot at 5 ms, +71.9 % × 603,980 ≈ +434,110 (603,980 is the fixed number for 300 mV, not the peak of the wave). The actual filter output is +436,232: a plain count has a resolution of only 2/256 = 0.78 %, whereas the decimation filter weights bits across adjacent slots and resolves the value to the LSB.
| Item | Value | Source |
|---|---|---|
| Output rate Fs | MFE_FCR.FREQ: 010 4 k (reset) · 011 8 k · 100 16 k · 101 32 kSPS → 256 / 128 / 64 / 32 bits per number | §7.6.5 |
| Code ↔ volts | V: DO = 1006633 × Vin × 2 · I/T: DO = 1006633 × Vin × PGA. The ×2 on V is a fixed scaling of the output code; the V analog path itself is a ×1 buffer (§1.1) | §3.6, §1.1 |
| Full scale | V 300 mV → 603,980 · I 275 mV at ×8 → 2,214,592 | §3.6 |
| Word | 24-bit two's complement, bits 2:0 tied to 0 (≈ 21 useful bits) | §5.4.2 |
| Passband at 4 kSPS | 0–1600 Hz, stopband 2400 Hz, ripple 0.001 dB up to 200 Hz | §3.4 |
| Filter delay, internal structure | not given. This page shows no delay and uses the simple count rule | not in spec |
Every analog circuit adds a small constant error called offset. It shifts the whole waveform up or down, so the middle of the wave is no longer at zero. The mains has no constant (DC) part, so any constant value in the samples is an error. The high-pass filter (HPF) removes it and puts the middle of the wave back on zero. It is on by default, and V, I and T all pass through the same filter.
RMS reads high. The meter would measure √(signal² + offset²) instead of the signal alone.
False energy. If both V and I carry an offset, their product adds a constant power that is billed even with no load.
HPF and the OFFSET register (Step 8) work together. The HPF is automatic and also follows offset that drifts with temperature. The OFFSET register is a fixed correction measured once at the factory.
| Item | Value | Source |
|---|---|---|
| Control | MFE_FCR.HPF (bit 4): 1 on (reset), 0 off | §7.6.5 |
| Position | after decimation; a second HPF follows calibration | Fig 5.1 |
| Offset before / after calibration | V 2 mV / <0.1 mV · I ×4 1 mV / <0.1 mV · I ×32 <0.1 mV / <0.01 mV (HPF off) | §3.3.1 p.33 |
| +60,000 offset used in the chart | example value (7.5 mV at the I pin), exaggerated for visibility | example |
| Corner frequency, settling time | not given | not in spec |
RCC_EN = 0, the reset value). The numbers pass through this block unchanged.Some meters measure current with a Rogowski coil instead of a CT. Its output must be converted back into the current shape, and that is what this block does. V and T are delayed by the same amount as the integrator, so all channels stay aligned.
What it is. A Rogowski coil is a coil placed around the wire, like a CT but without an iron core, so it keeps measuring correctly even at very high currents.
What it outputs. It does not tell how much current is flowing; it tells how fast the current is changing. Its output is largest when the current crosses zero (changing fastest) and zero when the current is at its top (momentarily not changing). That is why the coil signal is 5 ms ahead of the current in the chart below.
What the RCC does. It adds up those changes over time to rebuild the actual current, the same way adding up speed at every moment gives the distance travelled.
| Item | Value | Source |
|---|---|---|
| Control | MFE_FCR.RCC_EN (bit 5): 0 off (reset), 1 on | §7.6.5 |
| I channel | Integ + HPF | §5.1 |
| V, T channels | Delay comp only | Fig 5.1 |
| Integrator gain, delay value | not given | not in spec |
The CT is not perfect: its copy of the current comes out slightly early, by 0.8° (44.4 µs). Left uncorrected, the meter would measure the wrong angle between voltage and current, and therefore the wrong power. The phase shifter fixes this by delaying the I channel by the same amount.
Load delay: real, kept. With a fan-type load the real current is 30° (1.67 ms) behind the voltage. The meter must measure this, because it decides how much of the power is useful.
Sensor delay: error, removed. The CT's copy is 0.8° (44.4 µs) ahead of the real current, so without correction the chip would see 29.2° instead of 30°.
The fix. Delay the I channel by 46 steps of 0.977 µs = 44.9 µs. The chip's copy then matches the real current, still 30° behind the voltage.
| Item | Value | Source |
|---|---|---|
| Register | PSH_x_L/H (0x08/0x09), 10 bits used, 0–1023, reset 0 | §7.6.9 |
| Step, range | 0.976563 µs (1/1.024 MHz), max 999.02 µs = +17.9° at 50 Hz | §6.3.3 |
| Direction | delay only; delay whichever channel is early. Here PSH_I = 46 (0x02E), PSH_V = 0 | §6.3.3 |
| CT error 0.8° | example value | example |
| Error formula | ΔP/P ≈ ε × tan φ = 0.014 rad × tan 30° ≈ 0.8 % |
Component tolerances give every meter a slightly different gain and offset. During factory calibration a known voltage and current are applied, the error is measured, and two correction values are stored: an OFFSET that is subtracted and a GAIN factor that is multiplied. In this example the chip reads 0.5 % high with an offset of +1,536.
1. Offset. Apply zero input (inputs shorted). Whatever the chip reads is its offset; it is stored in the OFFSET register.
2. Gain. Apply an exactly known current, for example 10.000 A from a reference source. The ratio of true value to reading gives the gain correction, stored in the GAIN_ERR register.
3. From then on, every sample is corrected automatically: out = (in − offset) × gain correction. V, I and T each get their own pair of values.
| Item | Value | Source |
|---|---|---|
| Order | offset subtracted first, then gain multiplied | §6.3.2 |
| OFFSET_x_L (0x0A) | 8-bit signed, 1 LSB ≈ 63.6 µV at the pin, ±8 mV range. Example 0x03 = 190.7 µV = 1,536 codes at ×8 | §6.3.2 |
| GAIN_ERR_x (0x16/0x17) | 13 bits, 0x1000 = ×1.0 (reset), step 1/4096. Example 4076 (0xFEC) = ×0.99512 | §6.3.1 |
| Factory order | TRIM (reference) → OFFSET → GAIN_ERR → PSH | §6.3 |
| +0.5 % and +1,536 errors | example values | example |
Each channel (V, I, T) has its own three-wire interface. SCLK is the bit clock. SSYNC is a one-clock pulse marking the start of a word. SDATA carries the 24 bits, one per clock, least significant bit (b0) first. A new word is sent every 0.25 ms, on all three channels at the same time.
Bit order: the §5.4.2 text says b0 first (drawn here); Fig 5.4 shows the opposite. To be confirmed with Dolphin; the capture block should make the order configurable.
IRQ_V, IRQ_I and IRQ_T pins fire once, when each channel has finished starting up and its data is valid (up to 0.65 s after power-on). To know that each new number has arrived, our SoC's capture block watches SSYNC, collects the 24 bits, and then raises its own "sample ready" signal (an interrupt or a DMA request). That signal is drawn below as "Capture IRQ".The number written in the usual order: b23 on the left, b0 on the right. On the wire the order is reversed: b0 is sent first (see the timing diagram). b23 is the sign bit (0 = positive, 1 = negative). The three red bits (b2, b1, b0) are always 0; the chip ties them to 0 to save power.
1. Wait for the SSYNC pulse: a new number is starting.
2. On each of the next 24 SCLK rising edges, read one SDATA bit (▲ in the diagram): high = 1, low = 0.
3. Put the bits back in place, b0 first up to b23, to rebuild the 24-bit number.
4. Raise its own "sample ready" signal (interrupt or DMA request) so the number is stored in memory.
| Item | Value | Source |
|---|---|---|
| Enable | MFE_DCR.SERIAL = 1 (reset) | §7.6.3 |
| Protocol | DSP mode: SSYNC one SCLK high, data starts one SCLK later, 24 bits | §5.4.2 |
| Edges | chip changes SDATA on SCLK ↓, receiver samples on SCLK ↑ | §5.4.2 |
| Bit order | text says LSB first (drawn here); Fig 5.4 is labelled msb first. Confirm with Dolphin | conflict |
| Timing | setup 10 ns, hold 7 ns, output delay 10 ns from MCLK ↑ | §5.4.3 |
| SCLK speed, clocks per word, IRQ position | not given; drawn as 28 clocks per 0.25 ms | not in spec |
| AFE IRQ | IRQ_V/I/T = ACQ_x_READY, "channel reached acquisition mode": one event per channel after start-up (Tsbyu ≤ 0.65 s from power-down), not a per-sample strobe. Form MFE_ICR.INT_FORM, flag IFR_x (write 1 to clear), mask IMR_x | §4.2 Fig 4.2, §7.6.6–8 |
| Per-sample event | frame boundary = SSYNC. Our capture peripheral must generate the per-sample IRQ / DMA request | our SoC |
The table follows the selected instant through every stage, and ends with our firmware turning the number back into volts and amps. Move the cursor or press Animate to see all stages update together.
This path uses an ideal chip, so Steps 5 and 8 leave the numbers unchanged here; their effect was shown separately with example errors in those steps. Numbers are per 0.25 ms slot, so the final volts and amps match the mains values at the middle of the slot.
Every value used on this page, its derivation, and its source: Dolphin spec section, calculation, or example board value.
| Number | What it is | How it is calculated | Source |
|---|---|---|---|
| Mains, sensors and pins | |||
| 325.3 V | top of the 230 V mains wave | 230 × √2 = 230 × 1.414 | physics |
| 1 : 1,500 | voltage divider | chosen so 325 V becomes 217 mV, below the 300 mV limit | example |
| 216.8 mV | top of the V pin signal | 325.3 V ÷ 1,500 | calculated |
| 14.14 A | top of the 10 A current wave | 10 × 1.414 | physics |
| 2,500 : 1, 10 Ω | CT ratio and burden resistor | board choice | example |
| 56.6 mV | top of the I pin signal | 14.14 A ÷ 2,500 × 10 Ω | calculated |
| 30° / 1.67 ms | current lag of the example load (fan type) | 30 ÷ 360 × 20 ms | example |
| Amplifier and full scale | |||
| 300 mV | largest V pin signal (100 % of range) | given | §3.2.2.1 p.28 |
| 275 mV | largest I pin signal at gain ×8 | 0.55 V at ×4 ÷ 2 (limit halves when gain doubles) | §3.2.2.1, §3.6 p.42 |
| 2,200 mV | I full scale after the PGA | 275 mV × 8 | calculated |
| 72.3 % / 20.6 % | how full V / I are at their top | 216.8 ÷ 300 · 56.6 ÷ 275 | calculated |
| Conversion and timing | |||
| 4.096 MHz | master clock MCLK | given | §3.2.1 |
| 1,024,000 / s | bits per second from the converter | 4,096,000 ÷ 4 | §5.3 p.57 |
| 0.977 µs | time of one bit (and one phase-shift step) | 1 ÷ 1,024,000 s | §6.3.3 |
| 4,000 / s | numbers per second (Fs) | MFE_FCR.FREQ = 010 (reset value) | §7.6.5 p.82 |
| 0.25 ms | time for one number (one slot) | 1 ÷ 4,000 s | calculated |
| 256 | bits per number | 1,024,000 ÷ 4,000 | calculated |
| 80 | numbers per mains wave | 20 ms ÷ 0.25 ms (= 4,000 ÷ 50) | calculated |
| Output numbers | |||
| 1,006,633 | "volts to number" constant | given by Dolphin; equals 2²³ × 0.12 = 8,388,608 × 0.12 (derived, 0.12 set by the 1.25 V reference and internal scaling) | §3.6 p.42–43 derived |
| 603,980 | V number at 100 % (300 mV) | 1,006,633 × 0.3 × 2 | Table 3.2 p.43 |
| 2,214,593 | I number at 100 % (275 mV at ×8) | 1,006,633 × 0.275 × 8 (= 0.55 V × 4) | Table 3.1 p.42 |
| 24 bits, last 3 = 0 | size of each number | range −8,388,608 … +8,388,607 (2²³) | §5.4.2 p.59 |
| Corrections (Steps 5, 7, 8) | |||
| +60,000 | HPF example offset (7.5 mV at the I pin) | 60,000 ÷ (1,006,633 × 8) = 7.5 mV | example |
| 2 mV / 1 mV | real offset before calibration, V / I (×4) | given | §3.3.1 p.33 |
| 55.6 µs | one degree of the wave | 20 ms ÷ 360 | calculated |
| 44.4 µs | CT timing error (0.8°) | 0.8 × 55.6 µs | example |
| 46 | phase-shift steps (PSH_I) | 44.4 ÷ 0.977 = 45.5 → 46 | §6.3.3 |
| 44.9 µs | delay actually applied | 46 × 0.977 µs | calculated |
| 63.6 µV | one OFFSET register step | given | §6.3.2 p.62 |
| 1,536 | example offset in number units | 3 × 63.6 µV × 1,006,633 × 8 | example |
| 0.5 % | example chip gain error | chip reads × 1.005 | example |
| 4,076 | GAIN_ERR_I for a 0.5 % high chip | 4,096 ÷ 1.005 | §6.3.1 |
| Output interface and firmware | |||
| 96,000 bits / s | data on one SDATA wire | 24 bits × 4,000 | calculated |
| 0.65 s | max time after power-up before the AFE IRQ says a channel is ready | given (Tsbyu) | §4.5 |
| 0.00003104 A | firmware constant: amps per I number | 2,500 ÷ (1,006,633 × 8 × 10 Ω) | calculated |